1. Field of the Invention
The present invention relates to a ferroelectric memory. More particularly, the present invention relates to a ferroelectric memory including a ferroelectric capacitor used for a cell of the ferroelectric memory.
2. Description of the Related Art
A non-volatile memory can be attained by using a ferroelectric material as a capacitor insulating film of a memory cell. The ferroelectric material shows a hysteretic property. Data is accumulated in a non-volatile manner by using the hysteretic property. Such a non-volatile memory provides a random access at a time of about 100 ns. Therefore, it is referred to as an FeRAM (Ferroelectric Random Access Memory).
The FeRAM is expected to be applied in a field in which other non-volatile memories such as an EEPROM (Electric Erasable Programmable Read Only Memory) and a flash memory can not be used. This is because an operation of the FeRAM is much faster than those of a EEPROM and a flash memory, and the FeRAM can be operated at a low power supply voltage of about 3.5 V.
In a development of an FeRAM, it is important to develop a structure of an FeRAM in which a remnant polarization of a ferroelectric film used in a memory cell is not deteriorated, and a process for manufacturing it.
The FeRAM having a structure in which the remnant polarization of the ferroelectric film is not deteriorated is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 11-297942) corresponding to U.S. application Ser. No. 09/287,413. The disclosure of the above U.S. Application is incorporated herein by reference.
FIG. 1 shows the structure of the known FeRAM. The known FeRAM employs a planar type cell. The FeRAM is composed of a semiconductor substrate 501, a ferroelectric capacitor 502 provided above the semiconductor substrate 501, and a protecting film 503 of SiO2 provided on the ferroelectric capacitance element 502.
The ferroelectric capacitor 502 is composed of a lower electrode 504, an upper electrode 505 and a ferroelectric film 506 that is sandwiched by them. The upper electrode 505 is composed of IrO2 or Ir film.
A contact hole 507 is formed in the protecting film 503 through to the upper electrode 505.
Another contact hole 508 is formed in the protecting film 503 through to a diffusion layer 509 formed on the semiconductor substrate 501.
The ferroelectric capacitor 502 and the diffusion layer 509 are electrically connected to a wiring layer 510 through the contact holes 507 and 508, respectively.
The wiring layer 510 is constituted by a lamination film composed of a metal silicide film such as tungsten silicide, a titanium nitride film, an aluminum film, and a titanium nitride film. The metal silicide layer is connected to the upper electrode 505 and the diffusion layer 509.
The ferroelectric film 506 has a large remnant polarization. This is because the material included in the wiring layer 510 is not diffused to the ferroelectric film 506 through a high temperature annealing and thereby the ferroelectric film 506 is not deteriorated. Moreover, the thermally induced stress resulting from the wiring layer 510 has no influence on the ferroelectric film 506.
Here, it is necessary that the lower electrode 504 of the FeRAM is connected to a wiring layer for giving a potential to the electrode 504. It is desirable that this wiring layer is surely connected to the lower electrode 504.
However, how the wiring layer is connected to the lower electrode 504 is not noted in the above-mentioned Japanese Laid Open Patent Application (JP-A-Heisei, 11-297942) corresponding to the U.S. application Ser. No. 09/287,413.
With regard to the structure of the connection portion between the electrode and the wiring layer, other techniques are disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 11-8360, JP-A-Heisei, 11-163279, JP-A-Heisei, 6-125057 and JP-A-Heisei, 11-145422, and Japanese Patent Office Gazette (2926050).
We have investigated how the wiring layer should be connected to the electrode of the memory cell capacitor of the FeRAM. As a result, we obtain the following inventions.
Therefore, an object of the present invention is to protect the characteristics of a memory cell capacitor from being deteriorated and to surely connect a wiring to an electrode of the memory cell capacitor.
Another object of the present invention is to protect the characteristics of a memory cell capacitor from being deteriorated, in a ferroelectric memory employing a planar type cell, and to surely connect a wiring to an electrode of the memory cell capacitor.
Still another object of the present invention is to protect the characteristics of a memory cell capacitor from being deteriorated and to protect an electrode of the memory cell capacitor from being stripped.
Still another object of the present invention is to protect a wiring connected to an electrode of a memory cell capacitor from being stripped.
In order to achieve an aspect of the present invention, a ferroelectric memory is composed of a wiring layer including substantially no silicon, a bottom electrode coupled to the wiring layer, a ferroelectric film formed on the bottom electrode, a top electrode formed on the ferroelectric film, and a metal silicide layer coupled to the top electrode and located above the ferroelectric film.
In the ferroelectric capacitor, it is possible to suppress the deterioration of the ferroelectric film resulting from a annealing process carried out after the formation of the metal wiring. This is because the metal silicide film is formed above the ferroelectric film. The metal silicide film effectively protects the bad influence on the ferroelectric film caused by the thermal stress of the wiring. As a result, the deterioration of the ferroelectric film is not easily induced. Moreover, in the ferroelectric capacitor according to the present invention, it is possible to protect the strip of the films of the wiring and the lower electrode and also avoid the conductive defect in a contact to the lower electrode and the increase in resistance. This is because the lower electrode and the metal silicide are not in direct contact with each other.
The wiring and the ferroelectric film may be located on a same side of the bottom electrode. In the FeRAM employing the planar type cell, it is possible to suppress the deterioration of the ferroelectric film and further possible to protect the conductive defect in the contact to the lower electrode and the increase in the resistance.
The ferroelectric memory may be further composed of another metal silicide layer, wherein the wiring layer penetrates the other metal silicide layer.
In this case, the other metal silicide layer may cover at least a portion of the ferroelectric film. The other metal silicide layer suppress the deterioration of the ferroelectric film.
The ferroelectric memory may be further composed of another bottom electrode fabricated at the same time of the bottom electrode, another ferroelectric film coupled to the other bottom electrode, and another wiring layer coupled to the other bottom electrode. In this case, the other wiring layer penetrates the other ferroelectric film.
The other bottom electrode can be used as a conductive island to be connected to still another wiring layer. The other bottom electrode enlarges a facility for arranging elements and interconnections of the ferroelectric memory.
The ferroelectric memory may be further composed of another metal silicide layer fabricated at the same time of the metal silicide layer. In this case, the other wiring layer penetrates the other metal silicide layer.
The metal silicide layer may be formed of tungsten silicide.
Also, The top electrode may include an iridium oxide film and an iridium film. In this case, it is desirable that the iridium oxide film is formed on the ferroelectric film and the iridium film is formed on the iridium oxide film. Both of the iridium oxide film and the iridium are hard to react with metal silicide film. Therefore, the characteristics of the ferroelectric film is not deteriorated by the diffusion of silicon into the ferroelectric film.
The bottom electrode is desirably formed of platinum. The ferroelectric film formed on a platinum film have excellent characteristics.
In order to achieve another aspect of the present invention, a method of fabricating a ferroelectric memory is composed of forming a ferroelectric capacitor including:
a bottom electrode,
a ferroelectric film formed on the bottom electrode, and
a top electrode coupled to the ferroelectric film;
forming a metal silicide layer coupled to the top electrode and located above the ferroelectric film; and
forming a wiring layer including substantially no silicon and coupled to the bottom electrode.
The method may be further composed of
forming an interlayer insulating film on the ferroelectric capacitor;
forming a first contact hole through the interlayer insulating film to the top electrode. In this case, the forming the metal silicide layer includes forming a metal silicide film on the interlayer insulating film and the top electrode. The metal silicide film is coupled to the top electrode inside the contact hole. Also, the forming the wiring layer includes:
forming a second contact hole through the metal silicide film and the interlayer insulating film; and
forming the wiring layer through the second contact hole to the bottom electrode.
The forming the second contact hole may include:
selectively removing a selected portion of the metal silicide film; and
forming the second contact hole whose width is narrower than that of the selected portion.
Also, the forming the metal silicide layer may include etching the metal silicide film to form the metal silicide layer.
The top electrode may include an iridium oxide film coupled to the ferroelectric film, and an iridium film coupled to the iridium oxide film.
In this case, the method may be further composed of etching a surface portion of the iridium film before the forming the metal silicide layer. The metal silicide film is coupled to the surface portion. The removal of the surface portion reduce a contact resistance between the metal silicide layer and the top electrode.
The method may be further composed of:
forming another bottom electrode at the same time of the bottom electrode;
forming another ferroelectric film coupled to the other bottom electrode;
forming another metal silicide layer; and
forming another wiring layer coupled to the other bottom electrode. The other wiring layer penetrates the other ferroelectric film and the other metal silicide film.
In this case, the method may be further composed of:
forming a metal silicide film connected to the top electrode; and
etching the metal silicide film to form the metal silicide layer and the other metal silicide layer.